A synchronous digital system uses a periodic clock signal to coordinate when stored state is allowed to change.

Instead of remaining transparent while a clock level is active, an edge-triggered flip-flop captures its input only around a clock transition.

Clock edges

A clock alternates between logical low and high. The transition from low to high is a rising edge; the transition from high to low is a falling edge.

Digital circuits can be designed so that state updates occur on one chosen edge.

D flip-flop

A D flip-flop copies its data input $D$ to output $Q$ at the active clock edge and preserves that value until the next active edge.

at active edge: Q ← D
between edges:  Q holds

Why edges help

Combinational logic has most of a clock period to calculate new values from the current state. The next edge then captures those results together, separating computation from state update.

Real flip-flops still have setup, hold and propagation timing requirements; a clock does not make physical delays disappear.