A simple processor model fetches one instruction, decodes it, executes it and then starts the next instruction. A pipeline improves throughput by overlapping stages from several instructions.

A simplified pipeline might contain

fetch -> decode -> execute -> memory -> write-back

while several instructions occupy different stages at the same time.

Throughput versus latency

Pipelining does not necessarily make one instruction complete in fewer stages. Its main benefit is throughput: once the pipeline is full, another instruction can complete frequently because different stages work in parallel.

Dependencies create hazards

Overlap becomes difficult when one instruction depends on another.

A data hazard occurs when an instruction needs a result that an earlier instruction has not produced yet.

A: r1 = r2 + r3
B: r4 = r1 + r5

The processor can sometimes forward the result directly between pipeline stages. Otherwise it may insert a stall until the value is available.

Control hazards

Branches change the next instruction address.

if condition:
    jump target

The fetch stage may need to choose the next instruction before the branch condition has finished executing. Waiting for every branch to resolve would leave later pipeline stages idle and reduce throughput.

This is a control hazard.

Pipeline depth and penalties

Deeper pipelines can divide work into shorter stages and support higher operating frequencies, but they also increase the amount of in-flight work that can be affected by a wrong control-flow decision.

Keeping the pipeline busy

Modern processors combine several techniques to reduce stalls, including forwarding, scheduling, prediction and speculative execution.

The key idea is that instruction execution is not simply one completed instruction followed by the next. Once operations overlap, uncertainty and dependencies become performance problems that the microarchitecture must manage.