An enhancement nMOS transistor is commonly described using the gate-source voltage $V_{GS}$ and drain-source voltage $V_{DS}$.

When

$$V_{GS}<V_{TH},$$

the device is in cutoff and the drain current is ideally negligible.

When a channel exists and

$$0\le V_{DS}<V_{GS}-V_{TH},$$

the device is in the triode or linear region. A simple long-channel model is

$$I_D=k\left[(V_{GS}-V_{TH})V_{DS}-\frac{V_{DS}^2}{2}\right],$$

where $k$ is a device parameter that sets the current scale.

When

$$V_{DS}\ge V_{GS}-V_{TH},$$

the channel pinches off near the drain and the device enters saturation, with the idealized relation

$$I_D\approx \frac{k}{2}(V_{GS}-V_{TH})^2.$$

Real MOSFETs depart from these equations through channel-length modulation, parasitic resistances and other effects. The piecewise model nevertheless separates the regimes needed for switching and analog design.