A CMOS inverter uses a complementary pair of MOSFETs: a p-channel transistor connects the output toward the positive supply and an n-channel transistor connects it toward ground.

When the input is low, the pMOS is on and the nMOS is off, so the output is driven high. When the input is high, the nMOS is on and the pMOS is off, so the output is driven low.

This complementary action implements logical NOT while ideally avoiding a steady direct path from supply to ground in either static logic state.

During a transition, both devices can conduct temporarily and internal capacitances must charge or discharge. Dynamic power therefore grows with switching activity, capacitance, supply voltage and frequency, approximately as

$$P_{dyn}\propto C V_{DD}^2 f.$$

CMOS logic connects semiconductor device behavior to Boolean gates: digital voltage levels emerge from transistor switching rather than from abstract logic alone.