On a multicore processor, different cores may cache copies of the same memory location. Cache coherence keeps those copies sufficiently consistent that ordinary shared-memory programming remains meaningful.

Suppose cores A and B both cache the line containing x. If A writes a new value while B keeps using an old cached copy indefinitely, the machine would expose contradictory values for the same address.

Coherence protocols therefore coordinate ownership of cache lines. A common write-invalidate strategy requires a core that will modify a shared line to obtain exclusive ownership and invalidate other cached copies before the write becomes globally visible through the coherence mechanism.

Coherence is usually maintained at cache-line granularity, not individual-variable granularity. Writing one byte can therefore trigger coherence traffic for the whole line.

Coherence does not mean every load from every core observes all writes in one universal real-time order. Memory consistency separately specifies which orderings a program may observe and which synchronization operations constrain them.

Cache coherence makes shared cached data possible; it also introduces traffic and contention when many cores repeatedly write the same lines.