Pipelining overlaps stages of different instructions. A superscalar processor goes further by issuing multiple independent instructions to execution units during the same cycle when resources and dependencies permit it.

Consider

r1 = r2 + r3
r4 = r5 * r6
r7 = r1 + r8

The multiply producing r4 is independent of the first addition and can overlap it. The third instruction cannot use r1 until the first produces it.

An out-of-order processor looks beyond a stalled instruction for later instructions whose operands are ready. It may execute those operations early while preserving the program's required architectural result.

False dependencies caused only by reuse of register names can be removed with register renaming, allowing otherwise independent operations to proceed simultaneously.

Completed results are normally committed in an order that preserves precise program behavior, even though internal execution occurred in a different order.

Instruction-level parallelism is limited by true data dependencies, branches, available execution units and the finite window of instructions the processor can inspect. It accelerates one instruction stream without requiring the programmer to create threads.